Recently, as the unit area of a chip gets smaller and a critical dimension is gradually reduced with the high integration of semiconductor devices, the photolithography process realizing patterns on a wafer becomes more and more important.
In general, a photolithography process is performed by first coating a photoresist on a wafer, and then photo-exposing and developing the coated photoresist. After each unit process, a bake process is further performed to increase the hardness of the photoresist on the wafer.
A related art photolithography process, where the photoresist layer is patterned using a light source such as ArF, KrF and F2 excimer laser, has several limitations in implementing a fine pattern such as a gate.
In addition, it may be difficult for the related art photolithography process to realize a linewidth of several nanometers due to a limitation of an optical system and a resolution limit of a photoresist polymer itself.
Furthermore, it may be difficult to apply the related art photolithography process to a method of forming a hole or an interconnection line in a multi-layered structure.